M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Quality versus Cost Analysis for 3D Stacked ICs (April 2014), 32nd IEEE VLSI Test Symposium (VTS 2014), 13-17 April 2014, Napa, USA [Conference Proceedings]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Impact of Mid-Bond Testing in 3D Stacked ICs (October 2013), 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Using 3D-COSTAR for 2.5D Test Cost Optimization (October 2013), IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA [Conference Paper]

M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, 3D-COSTAR: A Cost Model For 3D Stacked ICs (November 2012), Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012), 8-9 November 2012, Anaheim, USA [Conference Proceedings]