C.R. Lageweg

NameC.R. Lageweg
First NameCasper
E-mail
Author TypePhd Student
AffiliationTU Delft

Publications

C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana, High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology 828_high_radix_addition_via_conditional_charge_transport_in_sing.pdf (July 2005), 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece [Conference Paper]
C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana, Design Methodology for Single Electron Based Building Blocks 825_design_methodology_for_single_electron_based_building_blocks.pdf (July 2005), 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Buffer Design Trade-Offs for Single Electron Logic Gates 824_buffer_design_tradeoffs_for_single_electron_logic_gates.pdf (July 2005), 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan , Best Paper Award [Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, Addition Related Arithmetic Operations via Controlled Transport of Charge 854_addition_related_arithmetic_operations_via_controlled_transp.pdf (March 2005), IEEE Transactions on Computers (TC), volume 54, issue 3 [Journal Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, On Effective Computation with Nanodevices: A single Electron Tunneling Case Study 990_on_effective_computation_with_nanodevices_a_single_electron.pdf (October 2004), International Semiconductor Conference (CAS 2004), 4-6 October 2004, Sinaia, Romania , Invited Paper [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Binary Addition based on Single Electron Tunneling Devices 904_binary_addition_based_on_single_electron_tunneling_devices.pdf (August 2004), 4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single Electron Encoded Latches and Flip-Flops 927_single_electron_encoded_latches_and_flipflops.pdf (June 2004), IEEE Transactions on Nanotechnology (TNANO), volume 3, issue 2 [Journal Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Evaluation Methodology for Single Electron Encoded Threshold Logic Gates 1050_evaluation_methodology_for_single_electron_encoded_threshol.pdf (December 2003), International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC 2003), 1-3 December 2003, Darmstadt, Germany [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single Electron Encoded SET Memory Elements 1073_single_electron_encoded_set_memory_elements.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Building Blocks for Electron Counting Arithmetic 1074_building_blocks_for_electron_counting_arithmetic.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge 1027_on_computing_addition_related_arithmetic_operations_via_con.pdf (June 2003), 16th IEEE Symposium on Computer Arithmetic (ARITH-16 2003), 15-18 June 2003, Santiago de Compostela, Spain [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A family of single electron static buffered Boolean logic 1137_a_family_of_single_electron_static_buffered_boolean_logic.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, 7/3 and 7/2 Counters implemented in single electron technology 1135_73_and_72_counters_implemented_in_single_electron_technol.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A full adder implementation using SET based linear threshold gates 1088_a_full_adder_implementation_using_set_based_linear_threshol.pdf (September 2002), 9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Static buffered SET based logic gates 1099_static_buffered_set_based_logic_gates.pdf (August 2002), 2nd IEEE Conference on Nanotechnology (IEEE-NANO 2002), 26-28 August 2002, Washington DC, USA [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single electron encoded logic circuits 1213_single_electron_encoded_logic_circuits.pdf (November 2001), 4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A turnstile based single electron memory element 1212_a_turnstile_based_single_electron_memory_element.pdf (November 2001), 4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Digital to analog conversion performed in single electron technology 1228_digital_to_analog_conversion_performed_in_single_electron_t.pdf (October 2001), 1st IEEE Conference on Nanotechnology (IEEE-NANO 2001), 28-30 October 2001, Maui, USA [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Achieving fanout capabilities in single electron encoded logic networks 1227_achieving_fanout_capabilities_in_single_electron_encoded_lo.pdf (October 2001), 6th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2001), 22-25 October 2001, Shanghai, China [Conference Paper]
C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A linear threshold gate implementation in single electron technology 1202_a_linear_threshold_gate_implementation_in_single_electron_t.pdf (April 2001), IEEE Computer Society Workshop on VLSI (WVLSI 2001), 19-20 April 2001, Orlando, USA [Conference Paper]