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J. Verbree

NameJ. Verbree
First NameJouke
E-mail
Author TypeMsc Student
AffiliationTU Delft

Publications

M. Taouil, S. Hamdioui, J. Verbree, E.J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs 249_on_maximizing_the_compound_yield_for_3d_wafertowafer_stack.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
E.J. Marinissen, C.C. Chi, J. Verbree, M. Konijnenburg, 3D DfT Architecture for Pre-Bond and Post-Bond Testing (November 2010), IEEE International Conference on 3D System Integration (3DIC 2010), 16-18 November 2010, Munich, Germany [Conference Paper]
J. Verbree, On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture (July 2010), [Msc Thesis]
J. Verbree, E.J. Marinissen, P. Roussel, D. Velenis, On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking (May 2010), 15th IEEE European Test Symposium (ETS 2010), 25-28 May 2010, Prague, Czech Republic [Conference Paper]
B. Noia, S.K. Goel, K. Chakrabarty, E.J. Marinissen, J. Verbree, Test-architecture optimization for TSV-based 3D stacked ICs (May 2010), 15th IEEE European Test Symposium (ETS 2010), 25-28 May 2010, Prague, Czech Republic [Conference Paper]
E.J. Marinissen, J. Verbree, M. Konijnenburg, A structured and scalable test access architecture for TSV-based 3D stacked ICs (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]
J. Verbree, E.J. Marinissen, P. Roussel, D. Velenis, Cost-Effectiveness of Wafer-to-Wafer 3D Chip Stacking with Matching Pre-Tested Wafers (March 2010), Design, Automation and Test in Europe (DATE 2010), 8-12 March 2010, Dresden, Germany , Poster at DATE 2010 Friday Workshop [Conference Paper]