I.S. Irobi

NameI.S. Irobi
First NameSandra
E-mailI.S.Irobi@tudelft.nl
Author TypePhd Student
AffiliationTU Delft

Publications

I.S. Irobi, Z. Al-Ars, S. Hamdioui, Testing for Parasitic Memory Effect in SRAMs 99_testing_for_parasitic_memory_effect_in_srams.pdf (November 2011), 20th Asian Test Symposium (ATS 2011), 20-23 November 2011, New Delhi, India [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs 61_memory_test_optimization_for_parasitic_bit_line_coupling_in_s.pdf (May 2011), 16th IEEE European Test Symposium (ETS 2011), 23-27 May 2011, Trondheim, Norway [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell, Influence of Parasitic Memory Effect on Single-Cell Faults in SRAMs 71_influence_of_parasitic_memory_effect_on_singlecell_faults_in.pdf (April 2011), 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 13-14 April 2011, Cottbus, Germany [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Detecting Memory Faults in the Presence of Bit Line Coupling in SRAM Devices 248_detecting_memory_faults_in_the_presence_of_bit_line_coupling.pdf (November 2010), IEEE International Test Conference (ITC 2010), 2-4 November 2010, Austin, USA [Conference Paper]
I.S. Irobi, Z. Al-Ars, S. Hamdioui, Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs 202_bit_line_coupling_memory_tests_for_singlecell_fails_in_sram.pdf (April 2010), 28th IEEE VLSI Test Symposium (VTS 2010), 19-22 April 2010, Santa Cruz, USA [Conference Paper]
I.S. Irobi, Z. Al-Ars, Worst-Case Bit Line Coupling Backgrounds for Open Defects in SRAM Cells 396_worstcase_bit_line_coupling_backgrounds_for_open_defects_in.pdf (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]
I.S. Irobi, B.H.H. Juurlink, On-chip Scratchpad Memory Size Prediction and Allocation for Multiprocess Embedded Applications 784_onchip_scratchpad_memory_size_prediction_and_allocation_for.pdf (November 2006), 17th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006), 23-24 November 2006, Veldhoven, The Netherlands [Conference Paper]