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Type Year Author Title
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Displaying 1676-1700 of 1700 result(s).
S. Vassiliadis, G.G. Pechanek, L.D. Larsen, C.J. Glossner, Array processor communication architecture with broadcast instructions (July 2000), filed in Europe [Patent]
S. Wong, S.D. Cotofana, S. Vassiliadis, Multimedia Enhanced General-Purpose Processors 1254_multimedia_enhanced_generalpurpose_processors.pdf (July 2000), IEEE International Conference on Multimedia and Expo (ICME 2000), 30 July - 2 August 2000, New York, USA [Conference Paper]
H. Gautama, A.J.C. van Gemund, On the Use of Lambda Distributions in Parallel Program Performance Prediction (June 2000), 6th Annual conference of the Advanced School for Computing and Imaging (ASCI 2000), 14-16 June 2000, Lommel, Belgium [Conference Paper]
H. Corporaal, Embedded processor design using transport triggered architectures (June 2000), International Workshop on Spectral Transforms and Logic Design for Future Digital Systems (SPECLOG 2000), 2-3 June 2000, Tampere, Finland [Conference Paper]
B.H.H. Juurlink, P. Kolman, F. Meyer auf der Heide, I. Rieping, Optimal Broadcast on Parallel Locality Models (June 2000), 7th International Colloquium on Structural Information and Communication Complexity (SIROCCO 2000), 20-22 June 2000, Laquila, Italy [Conference Paper]
A. Gonzalez Escribano, A.J.C. van Gemund, V. Cardenoso Payo, J. Alonso Lopez, D. Martin Garcia, A. Pedrosa Calvo, Measuring the Performance Impact of SP-restricted Programming in Shared-Memory Machines (June 2000), 4th International Conference on Vector and Parallel Processing (VECPAR 2000), 21-23 June 2000, Porto, Portugal [Conference Paper]
S. Vassiliadis, B. Blaner, T.L. Jeremiah, System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction (June 2000), filed in Europe [Patent]
P.G. D'Arcy, S. Jinturkar, C.J. Glossner, S. Vassiliadis, Multiple machine view execution in a computer system (June 2000), filed in USA [Patent]
A.G.M. Cilio, H. Corporaal, The Impact of Code Positioning on ILP Scheduling (June 2000), 6th Annual conference of the Advanced School for Computing and Imaging (ASCI 2000), 14-16 June 2000, Lommel, Belgium [Conference Paper]
S. Vassiliadis, S.D. Cotofana, P.T. Stathis, Block Based Compression Storage Expected Performance 1262_block_based_compression_storage_expected_performance.pdf (June 2000), 14th International Conference on High Performance Computing Systems and Applications (HPCS 2000), 14-17 June 2000, Victoria, Canada [Conference Paper]
T. Niculiu, C. Aktouf, S.D. Cotofana, Hierarchical interfaces for hardware/software systems 1263_hierarchical_interfaces_for_hardwaresoftware_systems.pdf (May 2000), 14th European Simulation Multiconference - Simulation and Modelling: Enablers for a Better Quality of Life (ESM 2000), 23-26 May 2000, Ghent, Belgium [Conference Paper]
A. Radulescu, A.J.C. van Gemund, Fast and effective task scheduling in heterogeneous systems 1265_fast_and_effective_task_scheduling_in_heterogeneous_systems.pdf (May 2000), 9th Heterogeneous Computing Workshop (HCW 2000), 1 May 2000, Cancun, Mexico [Conference Paper]
A.J. van de Goor, Z. Al-Ars, Functional memory faults: a formal notation and a taxonomy 1264_functional_memory_faults_a_formal_notation_and_a_taxonomy.pdf (April 2000), 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada [Conference Paper]
A. Smit, MOVE Processor Generator (April 2000), [Msc Thesis]
A.G.M. Cilio, H. Corporaal, Link-time effective whole-program optimizations (March 2000), Future Generation Computer Systems (FGCS), volume 16, issue 5 [Journal Paper]
G.G. Pechanek, S. Vassiliadis, Massively parallel multiple-folded clustered processor mesh array (March 2000), filed in USA [Patent]
S. Wong, S.D. Cotofana, S. Vassiliadis, General-Purpose Processor Huffman Encoding Extension 1268_generalpurpose_processor_huffman_encoding_extension.pdf (March 2000), International Conference on Information Technology: Coding and Computing (ITCC 2000), 27-29 March 2000, Las Vegas, USA [Conference Paper]
S.D. Cotofana, S. Vassiliadis, Signed digit addition and related operations with threshold logic 1269_signed_digit_addition_and_related_operations_with_threshold.pdf (March 2000), IEEE Transactions on Computers (TC), volume 49, issue 3 [Journal Paper]
A. Berlea, S.D. Cotofana, I. Athanasiu, C.J. Glossner, S. Vassiliadis, Garbage collection for the Delft Java Processor 1270_garbage_collection_for_the_delft_java_processor.pdf (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]
B. Blaner, S. Vassiliadis, Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache (February 2000), filed in USA [Patent]
B. Blaner, S. Vassiliadis, Compounding preprocessor for cache (February 2000), filed in Europe [Patent]
B. Blaner, S. Vassiliadis, scalable compound instruction set machine architecture (February 2000), filed in USA [Patent]
M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction 1274_array_based_structure_loop_transformations_for_cache_miss_r.pdf (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]
A. Gonzalez Escribano, A.J.C. van Gemund, V. Cardenoso Payo, Performance Trade-offs in Series-parallel Programming Models (January 2000), 8th International Workshop on Compilers for Parallel Computers (CPC 2000), January 2000, Aussois, France [Conference Paper]
P.G. D'Arcy, S. Jinturkar, C.J. Glossner, S. Vassiliadis, Compiler controlled dynamic scheduling of program instructions (January 2000), filed in Europe [Patent]
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