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Type Year Author Title
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Displaying 1451-1475 of 1700 result(s).
P.T. Stathis, S. Vassiliadis, S.D. Cotofana, D-SAB: A Sparse Matrix Benchmark Suite 1006_dsab_a_sparse_matrix_benchmark_suite.pdf (September 2003), 7th International Conference on Parallel Computing Technologies (PaCT 2003), 15-19 September 2003, Novosibirsk, Russia [Conference Paper]
S. Vassiliadis, N.J. Dimopoulos, J.F. Collard, A. Bode, Parallel Computer Architecture and Instruction-Level Parallelism - Topic Introduction (August 2003), 9th International Euro-Par Conference on Parallel Processing (Euro-Par 2003), 26-29 August 2003, Klagenfurt, Austria [Conference Paper]
P.T. Groen, Hardware Acceleration of the SRP Authentication Protocol 946_hardware_acceleration_of_the_srp_authentication_protocol.pdf (August 2003), [Msc Thesis]
R. Eggermont, PROSA: Profiling-based State Assignment for Low Power Dissipation 1007_prosa_profilingbased_state_assignment_for_low_power_dissi.pdf (August 2003), [Msc Thesis]
W. Lu, Designing TCP/IP Functions In FPGAs 1008_designing_tcpip_functions_in_fpgas.pdf (August 2003), [Msc Thesis]
Z. Al-Ars, A.J. van de Goor, Systematic memory test generation for dram defects causing two floating nodes 1024_systematic_memory_test_generation_for_dram_defects_causing.pdf (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]
D. Hofstee, Exploring Criticality Numbers For Kahn Process Networks 1009_exploring_criticality_numbers_for_kahn_process_networks.pdf (July 2003), [Msc Thesis]
A. Snirpunas, Mapping of Motion Estimation on a VLIW Processor Template (July 2003), [Msc Thesis]
Y. Luo, Task Transaction Layers for Multiprocessor Platforms 1012_task_transaction_layers_for_multiprocessor_platforms.pdf (July 2003), [Msc Thesis]
Yun Zhang, A flexible pipelined processor simulator (July 2003), [Msc Thesis]
R. Gao, Static Adaptation of the Fetch Size to Reduce Processor Memory Traffic (July 2003), [Msc Thesis]
G.K. Kuzmanov, G.N. Gaydadjiev, S. Vassiliadis, Loading rm-code: Design Considerations 1015_loading_rmcode_design_considerations.pdf (July 2003), 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece [Conference Paper]
D. Bao Linh, Vectorization of Digital Filters for CVP 1016_vectorization_of_digital_filters_for_cvp.pdf (July 2003), [Msc Thesis]
Y. Wu, Benchmarking Real-Time Network Processing 1017_benchmarking_realtime_network_processing.pdf (July 2003), [Msc Thesis]
B. An, Vectorization of MPEG4 Kernels on the CVP 1018_vectorization_of_mpeg4_kernels_on_the_cvp.pdf (July 2003), [Msc Thesis]
S. Vassiliadis, G.N. Gaydadjiev, K.L.M. Bertels, E. Moscu Panainte, The Molen Programming Paradigm 1019_the_molen_programming_paradigm.pdf (July 2003), 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece [Conference Paper]
S. Vassiliadis, S. Wong, S.D. Cotofana, Microcode Processing: Positioning and Directions 1020_microcode_processing_positioning_and_directions.pdf (July 2003), IEEE Micro, volume 23, issue 4 [Journal Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs 1021_a_fault_primitive_based_analysis_of_linked_faults_in_rams.pdf (July 2003), 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, USA [Conference Paper]
D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs 1022_highlevel_energy_estimation_for_armbased_socs.pdf (July 2003), 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece [Conference Paper]
C.J. Glossner, S. Jinturkar, M. Moudgill, E. Hokenek, M.J. Schulte, S. Vassiliadis, Sandbridge Software Tools (July 2003), 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece [Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott, A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder 1025_adelta_a_64bit_high_speed_compact_hybrid_dynamiccmos.pdf (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]
M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, Color Space Conversion for MPEG Decoding on FPGA-augmented TriMedia Processor 1026_color_space_conversion_for_mpeg_decoding_on_fpgaaugmented.pdf (June 2003), 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands [Conference Paper]
S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge 1027_on_computing_addition_related_arithmetic_operations_via_con.pdf (June 2003), 16th IEEE Symposium on Computer Arithmetic (ARITH-16 2003), 15-18 June 2003, Santiago de Compostela, Spain [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, CMOS Implementation of Generalized Threshold Functions (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]
G.A. Fossung, Performance Evaluation of Adders on FPGAs (June 2003), [Msc Thesis]
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