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Type Year Author Title
Displaying 1626-1629 of 1629 result(s).
M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction 1274_array_based_structure_loop_transformations_for_cache_miss_r.pdf (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]
A. Gonzalez Escribano, A.J.C. van Gemund, V. Cardenoso Payo, Performance Trade-offs in Series-parallel Programming Models (January 2000), 8th International Workshop on Compilers for Parallel Computers (CPC 2000), January 2000, Aussois, France [Conference Paper]