Publications

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Type Year Author Title
Displaying 1401-1425 of 1625 result(s).
T. Niculiu, S.D. Cotofana, Hierarchical Reconfigurable Simulated Intelligence Templates (June 2003), IASTED International Conference on Intelligent Systems and Control (ISC 2003), 25–27 June 2003, Salzburg, Austria [Conference Paper]
L. Neuberg, K.L.M. Bertels, Heterogeneous Trading Agents 1030_heterogeneous_trading_agents.pdf (May 2003), Complexity, volume 8, issue 5 [Journal Paper]
P. Celinski, S.D. Cotofana, J.F. Lopez, S.F. Al-Sarawi, D. Abbott, State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications 1031_stateoftheart_in_cmos_thresholdlogic_vlsi_gate_implemen.pdf (May 2003), SPIE International Symposium on Microtechnologies for the New Millennium, 19-21 May 2003, San Agustín, Gran Canaria, Spain , Invited Paper [Conference Paper]
P. Celinski, S.D. Cotofana, D. Abbott, Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic 1033_area_efficient_high_speed_parallel_counter_circuits_using.pdf (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]
M.J. Geuzebroek, A.J. van de Goor, TPI for improving PR Fault Coverage of Boolean and Three-State Circuits 1034_tpi_for_improving_pr_fault_coverage_of_boolean_and_threest.pdf (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]
S. Hamdioui, R. Wadsworth, J.D. Reyes, A.J. van de Goor, Importance of Dynamic Faults for New SRAM Technologies 1035_importance_of_dynamic_faults_for_new_sram_technologies.pdf (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]
M.D. Padure, S.D. Cotofana, S. Vassiliadis, Design and Experimental Results of a CMOS Flip-Flop Featuring Embedded Threshold Logic (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]
A.J. van de Goor, Testing (embedded) memories : new fault models, test, Dft, BIST, BISR and industrial results (May 2003), 8th IEEE European Test Workshop (ETW 2003), 25-28 May 2003, Maastricht, The Netherlands [Conference Paper]
P.T. Stathis, S. Vassiliadis, S.D. Cotofana, A Hierarchical Sparse Matrix Storage Format for Vector Processors 1038_a_hierarchical_sparse_matrix_storage_format_for_vector_proc.pdf (April 2003), 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France [Conference Paper]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests 1039_dynamic_faults_in_randomaccessmemories_concept_fault_mo.pdf (April 2003), Journal of Electronic Testing: Theory and Applications (JETTA), volume 19, issue 2 [Journal Paper]
S. Hamdioui, A.J. van de Goor, M. Rodgers, Detecting intra-word faults in word-oriented memories 1040_detecting_intraword_faults_in_wordoriented_memories.pdf (April 2003), 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, USA [Conference Paper]
T. Niculiu, S.D. Cotofana, Concurrent Engineering for Intelligent Simulation (April 2003), European Concurrent Engineering Conference (ECEC 2003), 14-16 April 2003, Plymouth, UK [Conference Paper]
D. Burileanu, M. Sima, C. Negrescu, V. Croitoru, Robust Recognition of Small-Vocabulary Telephone-Quality Speech (April 2003), 2nd Conference on Speech Technology and Human-Computer Dialogue (SPeD 2003), 10-11 April 2003, Bucharest, Romania [Conference Paper]
B.H.H. Juurlink, P. Kolman, F. Meyer auf der Heide, I. Rieping, Optimal Broadcast on Parallel Locality Models 1043_optimal_broadcast_on_parallel_locality_models.pdf (April 2003), Journal of Discrete Algorithms (JDA), volume 1, issue 2 [Journal Paper]
Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation 1044_optimizing_stresses_for_testing_dram_cell_defects_using_ele.pdf (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]
Z. Al-Ars, A.J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs 1046_static_and_dynamic_behavior_of_memory_cell_array_spot_defec.pdf (March 2003), IEEE Transactions on Computers (TC), volume 52, issue 3 [Journal Paper]
I. Schanstra, A.J. van de Goor, Consequences of RAM bitline twisting for test coverage 1047_consequences_of_ram_bitline_twisting_for_test_coverage.pdf (March 2003), Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany [Conference Paper]
O. Bonorden, B.H.H. Juurlink, I. von Otte, I. Rieping, The Paderborn University BSP (PUB) Library 1048_the_paderborn_university_bsp_pub_library.pdf (February 2003), Parallel Computing, volume 29, issue 2 [Journal Paper]
I. Schanstra, A.J. van de Goor, Logical and topological testing of scrambled RAMs (February 2003), 4th IEEE Latin American Test Workshop (LATW 2003), 16-19 February 2003, Natal, Brazil [Conference Paper]
A.J. van de Goor, Introduction (January 2003), Book Title "Testing of Digital Systems", Published by Cambridge University Press [Book Chapter]
A.J. van de Goor, Memory Testing (January 2003), Book Title "Testing of Digital Systems", Published by Cambridge University Press [Book Chapter]
S. Wong, B. Stougie, S.D. Cotofana, Alternatives in FPGA-based SAD Implementations 1129_alternatives_in_fpgabased_sad_implementations.pdf (December 2002), 1st IEEE International Conference on Field-Programmable Technology (FPT 2002), 16-18 December 2002, Hong Kong, China [Conference Paper]