I.O. Agbo, M. Taouil, D.H.P. Kraak, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier (April 2017), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), volume 25, issue 4 [Journal Paper]

I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, Integral Impact of BTI and Voltage Temperature Variation on SRAM Sense Amplifier (April 2015), IEEE VLSI Test Symposium (VTS 2015), 27-29 April 2015, Napa, USA [Conference Proceedings]

I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P Weckx, P. Raghavan, F. Catthoor, BTI Analysis for High Performance and Low power SRAM Sense Amplifier (March 2015), 4th Workshop On Manufacturable and Dependable Multicore Architectures (MEDIAN 2015), 13 March 2015, Grenoble, France [Conference Paper]

I.O. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Impact of BTI on SRAM Sense Amplifier in the Presence of Temperature and Process Variation (September 2014), Joint MEDIAN–TRUDEVICE Open Forum, 30 September 2014, Amsterdam, The Netherlands [Conference Proceedings]

M.S. Khan, I.O. Agbo, S. Hamdioui, H. Kukner, B Kaczer, P. Raghavan, F. Catthoor, Bias Temperature Instability analysis of FinFET based SRAM cells (March 2014), Design, Automation & Test in Europe (DATE 2014), 24-28 March 2014, Dresden, Germany [Conference Proceedings]

H. Kukner, M.S. Khan, S. Hamdioui, P. Raghavan, F. Catthoor, Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates (March 2014), IEEE Transactions on Reliability (TR), volume 14, issue 1 [Journal Paper]

M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Bias temperature instability analysis in SRAM decoder (May 2013), 18th IEEE European Test Symposium (ETS 2013), 27-31 May 2013, Avignon, France [Conference Paper]

M.S. Khan, S. Hamdioui, M. Taouil, H. Kukner, P. Raghavan, F. Catthoor, Impact of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder Reliablity (December 2012), International Design & Test Symposium (IDT 2012), 15-17 December 2012, Doha, Qatar [Conference Proceedings]

M.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis (October 2012), IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 3-5 October 2012, Austin, USA [Conference Paper]

M.S. Khan, S. Hamdioui, H. Kukner, F. Catthoor, P. Raghavan, BTI Impacts on Logical Gates in Nano-scale CMOS Technology (April 2012), 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), 18-20 April 2012, Tallinn, Estonia [Conference Paper]

A.J. van de Goor, H. Kukner, S. Hamdioui, Optimizing Memory BIST Address Generator Implementations (April 2011), 6th International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2011), 6-8 April 2011, Athens, Greece , Best Paper Award [Conference Paper]

A.J. van de Goor, S. Hamdioui, H. Kukner, Generic, Orthogonal and Low-Cost March Element-based Memory BIST (January 2011), IEEE International Test Conference (IEEE ITC), 20-22 Sept, Anaheim, CA, USA [Conference Proceedings]

H. Kukner, Generic March Element based Memory BIST (September 2010), [Msc Thesis]