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Type Year Author Title
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Displaying 701-725 of 1700 result(s).
D. Borodin, Performance-Oriented Fault Tolerance in Computing Systems 279_performanceoriented_fault_tolerance_in_computing_systems.pdf (January 2010), [Phd Thesis]
T. Marconi, K.L.M. Bertels, G.N. Gaydadjiev, A Novel Logic Element for Power Reduction in FPDs 280_a_novel_logic_element_for_power_reduction_in_fpds.pdf (January 2010), Technical Report, Computer Engineering Lab [Technical Report]
T. Marconi, D. Theodoropoulos, K.L.M. Bertels, G.N. Gaydadjiev, A Novel HDL Coding Style for Power Reduction in FPGAs 281_a_novel_hdl_coding_style_for_power_reduction_in_fpgas.pdf (January 2010), Technical Report, Computer Engineering Lab [Technical Report]
E. Gabdulkhakov, Performance analysis of SCISM organization applied to the IA-32 architecture 282_performance_analysis_of_scism_organization_applied_to_the_ia.pdf (January 2010), [Msc Thesis]
O.S. Dragomir, K.L.M. Bertels, K-Loops: Loop Skewing for Reconfigurable Architectures 366_kloops_loop_skewing_for_reconfigurable_architectures.PDF (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
G.K. Kuzmanov, M. Taouil, Reconfigurable Sparse/Dense Matrix-Vector Multiplier 367_reconfigurable_sparsedense_matrixvector_multiplier.PDF (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
Z. Nawaz, T.P. Stefanov, K.L.M. Bertels, Efficient hardware generation for dynamic programming problems 368_efficient_hardware_generation_for_dynamic_programming_proble.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
M.A. Wahlah, K.G.W. Goossens, 3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip 369_3tier_reconfiguration_model_for_fpgas_using_hardwired_netwo.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
M. Alvarez, A. Ramirez, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, M. Valero, Scalability of Macroblock-level Parallelism for H.264 Decoding 370_scalability_of_macroblocklevel_parallelism_for_h264_decodi.pdf (December 2009), 15th International Conference on Parallel and Distributed Systems (ICPADS 2009), 8-11 December 2009, Shenzhen, China [Conference Paper]
T. Marconi, Y. Lu, K.L.M. Bertels, G.N. Gaydadjiev, A Novel Fast Online Placement Algorithm on 2D Partially Reconfigurable Devices 371_a_novel_fast_online_placement_algorithm_on_2d_partially_reco.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
D. Ludovici, A. Strano, D. Bertozzi, Architecture Design Principles for the Integration of Synchronization Interfaces into Network-on-Chip Switches 372_architecture_design_principles_for_the_integration_of_synchr.pdf (December 2009), 2nd ACM/IEEE International Workshop on Network-on-Chip Architectures (NoCArc 2009), 12 December 2009, New York, USA [Conference Paper]
A. Shahbahrami, M. Ahmadi, S. Wong, K.L.M. Bertels, A New Approach to Implement Discrete Wavelet Transform using Collaboration of Reconfigurable Elements 373_a_new_approach_to_implement_discrete_wavelet_transform_using.pdf (December 2009), International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), 9-11 December 2009, Cancun, Mexico [Conference Paper]
C. van der Bok, M. Taouil, P. Afratis, I. Sourdis, The TU Delft Sudoku Solver on FPGA 374_the_tu_delft_sudoku_solver_on_fpga.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia , 2nd prize FPT-2009 Design Competition Award [Conference Paper]
V.M. Sima, K.L.M. Bertels, Runtime memory allocation in a heterogeneous reconfigurable platform 375_runtime_memory_allocation_in_a_heterogeneous_reconfigurable.pdf (December 2009), International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), 9-11 December 2009, Cancun, Mexico [Conference Paper]
M. Fazlali, A. Zakerolhosseini, A. Shahbahrami, G.N. Gaydadjiev, High Speed Merged-datapath Design for Run-Time Reconfigurable Systems 376_high_speed_mergeddatapath_design_for_runtime_reconfigurabl.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
Z. Ahyadi, Experimental Analysis on ECC Schemes for Fault-Tolerant Hybrid Memories 377_experimental_analysis_on_ecc_schemes_for_faulttolerant_hybr.pdf (December 2009), [Msc Thesis]
K.A. Gbolagade, R. Chaves, L.A. Sousa, S.D. Cotofana, Residue-to-Binary Converters for the Moduli Set {2^{2n+1}-1, 2^{2n}, 2^{n}-1} 378_residuetobinary_converters_for_the_moduli_set_22n11.pdf (December 2009), 2nd International Conference On Adaptive Science & Technology (ICAST09), 14-16 December 2009, Accra, Ghana [Conference Paper]
K.A. Gbolagade, S.D. Cotofana, A Reverse Converter for the New 4-Moduli Set {2n+3,2n+2,2n+1,2n} 379_a_reverse_converter_for_the_new_4moduli_set_2n32n22n1.pdf (December 2009), 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS09), 13-19 December 2009, Yasmine Hammamet, Tunesia [Conference Paper]
M.A. Wahlah, K.G.W. Goossens, Composable And Persistent-State Application Swapping On FPGAs Using Hardwired Network on Chip 380_composable_and_persistentstate_application_swapping_on_fpga.pdf (December 2009), International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), 9-11 December 2009, Cancun, Mexico [Conference Paper]
S. Wong, F. Anjam, The Delft Reconfigurable VLIW Processor 381_the_delft_reconfigurable_vliw_processor.pdf (December 2009), 17th International Conference on Advanced Computing and Communications (ADCOM 2009), 14-17 December 2009, Bangalore, India , Invited Paper [Conference Paper]
K. Sigdel, M. Thompson, C. Galuzzi, A.D. Pimentel, K.L.M. Bertels, rSesae - A Generic System-Level Runtime Simulation Framework for Reconfigurable Architectures 382_rsesae__a_generic_systemlevel_runtime_simulation_framework.pdf (December 2009), International Conference on Field-Programmable Technology (FPT 2009), 9-11 December 2009, Sidney, Australia [Conference Paper]
A Rohani, H.R. Zarandi, M. Zandrahimi, New Switch Box Architecture for SEU Detection in SRAM-Based FPGAs 1687_new_switch_box_architecture_for_seu_detection_in_srambased.pdf (December 2009), 2nd International Conference on Computer Science and its Applications (CSA 2009), 10-12 December 2009, Jeju, South Korea [Conference Paper]
L. Mhamdi, PBC: A Partially Buffered Crossbar Packet Switch 383_pbc_a_partially_buffered_crossbar_packet_switch.pdf (November 2009), IEEE Transactions on Computers (TC), volume 50, issue 11 [Journal Paper]
I.V. Senin, L. Mhamdi, K.G.W. Goossens, Efficient Multicast Support in Buffered Crossbars using Networks on Chip 384_efficient_multicast_support_in_buffered_crossbars_using_netw.pdf (November 2009), Global Communications Conference (GLOBECOM 2009), 30 November - 4 December 2009, Honolulu, Hawaii, USA [Conference Paper]
M.A. Wahlah, K.G.W. Goossens, Run-Time FPGA Testing Using Hardwired Network on Chip (November 2009), 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), 26-27 November 2009, Veldhoven, The Netherlands [Conference Paper]
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