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Type Year Author Title
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Displaying 1101-1125 of 1700 result(s).
P. Diniz, E. Marques, K.L.M. Bertels, M.M. Fernandes, J.M.P. Cardoso, Proceedings of the Third International Workshop on Applied Reconfigurable Computing (April 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Proceedings]
C. Kachris, C. Kulkarni, Configurable Transactional Memory 624_configurable_transactional_memory.pdf (April 2007), 15th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), 23-25 April 2007, Napa, USA [Conference Paper]
K.L.M. Bertels, G.K. Kuzmanov, E. Moscu Panainte, G.N. Gaydadjiev, Y.D. Yankova, V.M. Sima, K. Sigdel, R.J. Meeuws, S. Vassiliadis, Profiling, Compilation, and HDL Generation within the hArtes Project 625_profiling_compilation_and_hdl_generation_within_the_hartes.pdf (April 2007), Workshop on Directions in FPGAs and Reconfigurable Systems: Adaptive Heterogeneous Systems-on-Chip and European Dimensions (DATE 2007 Workshop), 16-20 April 2007, Nice, France [Conference Paper]
C. Arbelo, A. Kanstein, S. Lopez, J.F. Lopez, M. Berekovic, R. Sarmiento, J.Y. Mignolet, Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264 Deblocking Filter 626_mapping_controlintensive_video_kernels_onto_a_coarsegrain.pdf (April 2007), Design, Automation and Test in Europe Conference and Exposition (DATE 2007), 16-20 April 2007, Nice, France [Conference Paper]
Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices 628_manifestation_of_precharge_faults_in_high_speed_dram_devices.pdf (April 2007), 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2007), 11-13 April 2007, Krakow, Poland [Conference Paper]
B. Spinean, Design Considerations for High Performance Vector Microarchitecture 629_design_considerations_for_high_performance_vector_microarchi.pdf (April 2007), [Msc Thesis]
C.B. Ciobanu, Customizing Vector Instruction Set Architectures 630_customizing_vector_instruction_set_architectures.pdf (April 2007), [Msc Thesis]
J.C. Bispo, I. Sourdis, J.M.P. Cardoso, S. Vassiliadis, Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues 631_synthesis_of_regular_expressions_targeting_fpgas_current_st.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
J.Y. Hur, T.P. Stefanov, S. Wong, S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects 632_systematic_customization_of_onchip_crossbar_interconnects.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
J.Y. Hur, S. Wong, S. Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs 633_partially_reconfigurable_pointtopoint_interconnects_in_vir.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
C. Galuzzi, K.L.M. Bertels, S. Vassiliadis, A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions 634_a_linear_complexity_algorithm_for_the_automatic_generation_o.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
F.J. Bouwens, M. Berekovic, A. Kanstein, G.N. Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
K. Wu, A. Kanstein, J. Madsen, M. Berekovic, MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture 636_mtadres_multithreading_on_coarsegrained_reconfigurable_ar.pdf (March 2007), 3rd International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007), 27-29 March 2007, Rio de Janeiro, Brazil [Conference Paper]
C.H. Meenderinck, S.D. Cotofana, An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology 637_an_analysis_of_basic_structures_for_effective_computation_in.pdf (March 2007), Romanian Journal of Information Science and Technology (ROMJIST), volume 10, issue 1 [Journal Paper]
E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, The Molen Compiler for Reconfigurable Processors 638_the_molen_compiler_for_reconfigurable_processors.pdf (February 2007), ACM Transactions on Embedded Computing Systems (TECS), volume 6, issue 1 [Journal Paper]
M. Ahmadi, S. Wong, Modified Collision Packet Classification Using CountingBloom Fillter In Tuple Space 639_modified_collision_packet_classification_using_countingbloom.pdf (February 2007), 25th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2007), 13-15 February 2007, Innsbruck, Austria [Conference Paper]
D.R.H. Calderón, G.N. Gaydadjiev, S. Vassiliadis, FPGA based implementation of Reconfigurable Universal Adders (January 2007), CE technical report [Technical Report]
S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder 768_opens_and_delay_faults_in_cmos_ram_address_decoder.pdf (December 2006), IEEE Transactions on Computers (TC), volume 55, issue 12 [Journal Paper]
B. Pourebrahimi, K.L.M. Bertels, M. Kandru, S. Vassiliadis, Market-based Resource Allocation in Grids 769_marketbased_resource_allocation_in_grids.pdf (December 2006), 2nd IEEE International Conference on e-Science and Grid Computing (e-Science 2006), 4-6 December 2006, Amsterdam, The Netherlands [Conference Paper]
S. Wong, F. Duarte, S. Vassiliadis, A Hardware Cache memcpy Accelerator 770_a_hardware_cache_memcpy_accelerator.pdf (December 2006), International Conference on Field Programmable Technology (FPT 2006), 13-15 December 2006, Bangkok, Thailand [Conference Paper]
Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs 771_influence_of_bit_line_coupling_and_twisting_on_the_faulty_be.pdf (December 2006), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 25, issue 12 [Journal Paper]
P. Ren, Wrapper design for the reuse of a NoC or other functional interconnect as test infrastructure 772_wrapper_design_for_the_reuse_of_a_noc_or_other_functional_in.pdf (December 2006), [Msc Thesis]
C. Kachris, S. Vassiliadis, Design of a Web Switch in a Reconfigurable Platform 773_design_of_a_web_switch_in_a_reconfigurable_platform.pdf (December 2006), 2nd ACM/IEEE Symposium on Architecture for Networking and Communications Systems (ANCS 2006), 3-5 December 2006, San Jose, USA [Conference Paper]
A. Shahbahrami, B.H.H. Juurlink, S. Vassiliadis, Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File 774_accelerating_color_space_conversion_using_extended_subwords.pdf (December 2006), 8th IEEE International Symposium on Multimedia (ISM 2006), 11-13 December 2006, San Diego, USA [Conference Paper]
D. Ludovici, Performance Analysis of RR and FQ Algorithms in Reconfigurable Routers 775_performance_analysis_of_rr_and_fq_algorithms_in_reconfigurab.pdf (December 2006), [Msc Thesis]
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