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Type Year Author Title
Displaying 251-275 of 1686 result(s).
N. Khammassi, J.C. Le Lann, Design and Implementation Of A Cache Hierarchy-Aware Task Scheduling For Parallel Loops On Multicore Architectures (February 2014), Third International conference on Parallel, Distributed Computing technologies and Applications (PDCTA 2014), 3-10 February 2014, Sydney, Australia [Conference Proceedings]
C. Wang, X. Li, X. Zhou, Y. Chen, K.L.M. Bertels, Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (poster) (February 2014), International Symposium on Field-Programmable Gate Arrays (FPGA), 26-28 February 2014, Monterey , abstract only [Conference Paper]
H. Pettenghi, S.D. Cotofana, L.A. Sousa, Efficient Method for Designing Modulo {2n ± k} Multipliers (January 2014), Journal of Circuits, Systems and Computers, volume 23, issue 1 [Journal Paper]
M Torquati, K.L.M. Bertels, S Karlsson, F Pacull, Smart Multicore Embedded Systems (January 2014), Published by Springer [Book]
I. Ashraf, K.L.M. Bertels, Memory Profiling for Intra-application Data-Communication Quantification: a Survey (January 2014), Technical Report, Computer Engineering Lab [Technical Report]
H. Mushtaq, Z. Al-Ars, K.L.M. Bertels, Accurate and Efficient Identification of Worst-Case Execution Time for Multicore Processors: A Survey 1400_accurate_and_efficient_identification_of_worstcase_executi.pdf (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
I.O. Agbo, M.S. Khan, S. Hamdioui, BTI Impact on SRAM Sense Amplifier 1418_bti_impact_on_sram_sense_amplifier.pdf (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
Z. Al-Ars, Reducing Random-Dopant Fluctuation Impact on Core-Speed and Power Variability in Many-Core Platforms (December 2013), 8th IEEE International Design and Test Symposium (IDT 2013), 16-18 December 2013, Marrakesh, Morocco [Conference Paper]
N. Aymerich, S.D. Cotofana, A. Rubio, Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell based Architectures 1364_controlled_degradation_stochastic_resonance_in_adaptive_ave.pdf (November 2013), IEEE Transactions on Nanotechnology (TNANO), volume 12, issue 6 [Journal Paper]
A. Beyranvand Nejad, A.M. Molnos, K.G.W. Goossens, A Unified Execution Model for Multiple Computation Models of Streaming Applications on a Composable MPSoC 1373_a_unified_execution_model_for_multiple_computation_models_o.pdf (November 2013), Journal of Systems Architecture - Embedded System Design (JSA), volume 59, issue 10 [Journal Paper]
J.M.P. Cardoso, T. Carvalho, J G de F. Coutinho, R Nobre, R. Nane, P. Diniz, Z. Petrov, W. Luk, K.L.M. Bertels, Controlling a complete hardware synthesis toolchain with LARA aspects 1394_controlling_a_complete_hardware_synthesis_toolchain_with_la.pdf (November 2013), Microprocessors and Microsystems (MICPRO), volume 37, issue 8 [Journal Paper]
L.M. Ciganda, P. Bernardi, M. Sonza Reorda, S. Hamdioui, An efficient method for the test of embedded memory cores during the operational phase (November 2013), 22nd Asian Test Symposium (ATS 2013), 18-21 November 2013, Yilan, Taiwan [Conference Proceedings]
M. Zandrahimi, Z. Al-Ars, An Overview of Power Reduction Techniques for Single and Multicore Systems 1433_an_overview_of_power_reduction_techniques_for_single_and_mu.pdf (November 2013), ICT.OPEN 2013, 27-28 November 2013, Eindhoven, The Netherlands [Conference Paper]
N. Cucu Laurenciu, S.D. Cotofana, A Direct Measurement Scheme of Amalgamated Aging Effects with Novel On-Chip Sensor 1359_a_direct_measurement_scheme_of_amalgamated_aging_effects_wi.pdf (October 2013), 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2013), 7-9 October 2013, Istanbul, Turkey [Conference Paper]
C. Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing 1387_heterogeneous_hardware_accelerator_architecture_for_streami.pdf (October 2013), International Conference on Advanced Technologies for Communications (ATC 2013), 16-18 October 2013, Hochiminh City, Vietnam [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Using 3D-COSTAR for 2.5D Test Cost Optimization 1388_using_3dcostar_for_25d_test_cost_optimization.pdf (October 2013), IEEE International 3D Systems Integration Conference (3DIC 2013), 2-4 October 2013, San Fransisco, USA [Conference Paper]
M. Taouil, S. Hamdioui, E.J. Marinissen, S Bhawmik, Impact of Mid-Bond Testing in 3D Stacked ICs 1389_impact_of_midbond_testing_in_3d_stacked_ics.pdf (October 2013), 16th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), 2-4 October 2013, New York, USA [Conference Paper]
D. Mirzoyan, S. Stuijk, B. Akesson, K.G.W. Goossens, Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation 1391_throughput_analysis_and_voltagefrequency_island_partitioni.pdf (October 2013), IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2012), 11-12 October 2012, Tampere, Finland [Conference Paper]
G. Roelofs, Design for Testability for Secure ICs (October 2013), [Msc Thesis]
N. Cucu Laurenciu, S.D. Cotofana, A Nonlinear Degradation Path Dependent End-of-Life Estimation Framework from Noisy Observations 1360_a_nonlinear_degradation_path_dependent_endoflife_estimati.pdf (September 2013), Microelectronics Reliability, volume 53, issue 9-11 [Journal Paper]